The chip was a huge, 7.6-million-transistor design with 850,000 equivalent logic gates in 246,000 placeable standard cells. The memory structures were very complex, with 136 individual custom RAMs (15 single-port RAMs, 119 dual-port RAMs and two CAMs) for a total of 700,000 bits of on-chip memory. The chip was fully synthesized from 128,000 lines of Verilog RTL code and required 264,000 lines of additional code to verify it with a total of more than 600 verification test cases. Three phase-locked-loop circuits generate the various clocks from a single reference clock. The main system clock runs at 100 MHz; the fastest clock runs at 125 MHz.

When we couldn't meet timing closure, because of our logic implementation, Silicon Perspective suggested that they could supply an applications engineer who could work on-site with us to demonstrate how its First Encounter tool could help us meet timing. While we gave him some required macro preplacements, we gave him no other resource or floor-planning guidance. The idea was to get the unbiased view of an outsider.

Silicon Perspective's applications engineer converted the library and technology files within an hour, and in a single afternoon he had completed the full place and route of this complex design. First Encounter automatically generated a floor plan similar to what we had derived over the last four months of work, yet it was generated in about a day.

Over the next day and a half, he duplicated our three major partitions. We saw enough promise in that work that we decided to apply some resources to verify the results. We had to be sure that First Encounter's placement could be routed in the Avanti tool environment and correlated with our timing results through our existing back-end flow.

Our tests proved that First Encounter's placement was routable and correlated within 10 to 12 percent for all nets. Cycle time for timing-closure iterations was reduced from days to a few hours. First Encounter gave quick feedback before committing to final routing.

Once we proved the correlation and saw the advantage of using First Encounter, the project team decided to abandon the physical implementation on which we had been focused for four months.

With our logic designers guiding the tool, we had timing closure on two of the three major modules within one week. The third module was finished in about three weeks, because we had to make structural changes.

By letting us get a big-picture view of entire huge modules, including all of the macros and memory blocks, we were better able to see where timing problems would occur and fix those areas right away. Our final product used 0.32-micron, five-metal-layer CMOS process technology and had a die area of 190 square mm. We fit it in a 420-pin BGA package.

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As CAD design manager at Advanced Micro Devices, Enterprise Computing Solutions (Sunnyvale, Calif.), Joaquin M. Bartra makes it his business to use the most efficient solutions to get designs out the door on time. "Up and running" is an immediate goal for his team.

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